Nanosheet devices can be viable device options instead of fin field-effect transistors (FinFETs). For example, nanowires or nanosheets can be used as the fin structure in a dual-gate, tri-gate or gate-all-around (GAA) FET device. Complementary metal-oxide semiconductor (CMOS) scaling can be enabled by the use of stacked nanowires and nanosheets, which offer superior electrostatics and higher current density per footprint area than FinFETs. Additionally, nanosheet devices are being pursued as a viable device option for the 5 nm node and beyond. Nanosheet formation relies on the selective removal of one semiconductor (e.g., SiGe) with respect to another (Si) to form the nanosheet and GAA structures.
In existing approaches, epitaxially grown doped source/drain regions in recessed portions of a semiconductor substrate can lead to source/drain punch-through through parasitic channel portions under the gates in nanosheet devices. Accordingly, there is a need for techniques and structures to improve isolation in order to prevent such source/drain shorts and reduce parasitic leakage for nanosheet structures.